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A 28-nm 8-bit Floating-Point Tensor Core-Based Programmable CNN Training Processor With Dynamic Structured Sparsity

https://doi.org/10.1109/JSSC.2023.3269148

Venkataramanaiah, Shreyas Kolala; Meng, Jian; Suh, Han-Sok; Yeo, Injune; Saikia, Jyotishman; Cherupally, Sai Kiran; Zhang, Yichi; Zhang, Zhiru; Seo, Jae-Sun (July 2023, IEEE Journal of Solid-State Circuits)

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A 1.23-GHz 16-kb Programmable and Generic Processing-in-SRAM Accelerator in 65nm

https://doi.org/10.1109/ESSCIRC55480.2022.9911440

Sridharan, Amitesh; Angizi, Shaahin; Cherupally, Sai Kiran; Zhang, Fan; Seo, Jae-Sun; Fan, Deliang (September 2022, 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC))

We present a generic and programmable Processing-in-SRAM (PSRAM) accelerator chip design based on an 8T-SRAM array to accommodate a complete set of Boolean logic operations (e.g., NOR/NAND/XOR, both 2- and 3-input), majority, and full adder, for the first time, all in a single cycle. PSRAM provides the programmability required for in-memory computing platforms that could be used for various applications such as parallel vector operation, neural networks, and data encryption. The prototype design is implemented in a SRAM macro with size of 16 kb, demonstrating one of the fastest programmable in-memory computing system to date operating at 1.23 GHz. The 65nm prototype chip achieves system-level peak throughput of 1.2 TOPS, and energy-efficiency of 34.98 TOPS/W at 1.2V.
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Improving DNN Hardware Accuracy by In-Memory Computing Noise Injection

https://doi.org/10.1109/MDAT.2021.3139047

Cherupally, Sai Kiran; Meng, Jian; Rakin, Adnan Siraj; Yin, Shihui; Seok, Mingoo; Fan, Deliang; Seo, Jae-Sun (August 2022, IEEE Design & Test)

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A 28nm 8-bit Floating-Point Tensor Core based CNN Training Processor with Dynamic Activation/Weight Sparsification

https://doi.org/10.1109/ESSCIRC55480.2022.9911359

Venkataramanaiah, Shreyas Kolala; Meng, Jian; Suh, Han-Sok; Yeo, Injune; Saikia, Jyotishman; Cherupally, Sai Kiran; Zhang, Yichi; Zhang, Zhiru; Seo, Jae-sun (September 2022, IEEE European Solid State Circuits Conference (ESSCIRC))

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Leveraging Noise and Aggressive Quantization of In-Memory Computing for Robust DNN Hardware Against Adversarial Input and Weight Attacks

https://doi.org/10.1109/DAC18074.2021.9586233

Cherupally, Sai Kiran; Rakin, Adnan Siraj; Yin, Shihui; Seok, Mingoo; Fan, Deliang; Seo, Jae-sun (December 2021, 2021 58th ACM/IEEE Design Automation Conference (DAC))

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A Smart Hardware Security Engine Combining Entropy Sources of ECG, HRV, and SRAM PUF for Authentication and Secret Key Generation

https://doi.org/10.1109/JSSC.2020.3010705

Cherupally, Sai Kiran; Yin, Shihui; Kadetotad, Deepak; Bae, Chisung; Kim, Sang Joon; Seo, Jae-sun (October 2020, IEEE Journal of Solid-State Circuits)
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ECG Authentication Neural Network Hardware Design with Collective Optimization of Low Precision and Structured Compression

https://doi.org/10.1109/ISCAS.2019.8702308

Cherupally, Sai Kiran; Srivastava, Gaurav; Yin, Shihui; Kadetotad, Deepak; Bae, Chisung; Kim, Sang Joon; Seo, Jae-sun (May 2019, IEEE International Symposium on Circuits and Systems (ISCAS))

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